1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a thin film transistor and a method for fabricating the same.
2. Background of the Related Art
Generally, a thin film transistor is used as a CMOS load transistor or a load transistor in an SRAM cell of 4M or 1M. The thin film transistor is also used as a switching device for switching a picture data signal in each pixel region in a liquid crystal display device.
Particularly, an off-current should be reduced and an on-current should increase when a PMOS thin film transistor is used as the load transistor in the SRAM cell. For this reason, power consumption of the SRAM cell may be reduced and its memory characteristic is increased, thereby obtaining the SRAM cell of high quality.
FIG. 1 is a sectional view of a thin film transistor of the background art. The thin film transistor includes an insulating layer 21, a gate electrode 22a formed on the insulating layer 21, and a gate insulating film 24 formed on the insulating layer 21 including the gate electrode 22a. A drain electrode D is formed on the gate insulating film 24 at a predetermined distance from the gate electrode 22a, and a source electrode S is formed on the gate insulating film 24 to overlap the gate electrode 22a and spaced apart from the drain electrode D. A channel region I and an offset region II are formed on the gate insulating film 24 between the source electrode S and the drain electrode D. The offset region II is formed between the drain electrode D and the gate electrode 22a. 
The method for fabricating the thin film transistor will be described with reference to FIGS. 2A to 2D. As shown in FIG. 2A, a first polysilicon layer 22 for a gate electrode of a bulk transistor is formed on the insulating layer or substrate 21. A photoresist is deposited on the first polysilicon layer 22 and then a mask pattern 23 is formed by exposure and development processes. Subsequently, the first polysilicon layer 22 is selectively removed by an etching process using the mask pattern 23 to form a gate electrode 22a, as shown in FIG. 2B.
As shown in FIG. 2C, a gate insulating film 24 is deposited on the insulating layer 21 including the gate electrode 22a. A second polysilicon layer 25 is then formed on the gate insulating film 24, which will be used to form the source and drain electrodes, an offset region and a channel region in the thin film transistor. Subsequently, a photoresist 26 is deposited on the second polysilicon layer 25 and then patterned by exposure and development processes.
As shown in FIG. 2D, a channel region and an offset region are defined by a photoresist pattern 26a of the patterned photoresist 26. Source and drain impurity ions or dopants are then implanted into the exposed second polysilicon layer 25 using the photoresist pattern 26a as a mask. Thus, a source electrode S is formed to partially overlap the gate electrode 22a and a drain electrode D is formed at a predetermined distance from the gate electrode 22a. The channel region I and the offset region II are formed between the source electrode S and the drain electrode D.
The above method for fabricating the thin film transistor has a problem that the on-current is small because the offset region is not affected by the gate voltage during the PMOS thin film transistor operation, thereby deteriorating reliability of the device.
An object of the present invention is to obviate at least the problems and disadvantages of the related art.
Another object of the present invention is to reduce the off current.
A further object of the present invention is to increase the on-current.
Still another object of the present invention is to provide a thin film transistor and a method for fabricating the same, in which an offset region is biased by a gate voltage to increase on-current, thereby improving on/off characteristic of a device.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a thin film transistor according to the present invention includes a first semiconductor layer formed on a substrate, insulating layer patterns formed at both ends of the first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer and the insulating layer patterns, a gate insulating film formed on the first and second semiconductor layers and the insulating layer patterns, and an active layer formed on the gate insulating film.
In another aspect, a method for fabricating the thin film transistor according to the present invention includes the steps of forming a first semiconductor layer on a substrate, forming insulating layer patterns on both ends of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the insulating layer patterns, forming a gate insulating film on the first and second semiconductor layers and the insulating layer patterns, and forming an active layer on the gate insulating film.
The present invention can be achieved in parts or a whole by a semiconductor device, comprising: a first conductive layer formed on a substrate; an offset spacer formed on the first conductor; a second conductive layer formed on the first conductive layer and the offset spacer; a first insulation layer formed over the substrate, the first and second conductive layers and the offset spacer; and an active layer formed on the first insulation layer, the active layer including source and drain electrodes, and channel and offset regions formed between the source and drain electrodes, the offset region being defined by the offset spacer.
The present invention can be also achieved in a whole or in parts by a semiconductor device, comprising: a first gate electrode formed on a substrate and having a first prescribed shape; a second gate electrode formed on the first gate electrode and having a second prescribed shape; an offset spacer formed in peripheral side surfaces of the second gate electrode and on the first gate electrode, the offset spacer having a height lower than the second gate electrode; an insulation film formed over the substrate, first and second gate electrodes and the offset spacer; and an active layer formed on the insulation film, the active layer including source and drain electrodes, and channel and offset regions formed between the source and drain electrodes, the offset region being defined by the offset spacer.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.